In the present day, three dimensional transistor devices are used to provide increased performance over planar transistors. Devices such as finFET devices and horizontal-Gate-All-Around (hGAA) FETs are formed from fin-shaped semiconductor regions extending perpendicularly from a substrate plane, such as the plane of a silicon wafer. Adjacent fins in such devices may be packed close to one another where a ratio of fin structure height:fin structure spacing may approach 10:1 at certain stages in processing, accounting for extra layers including polysilicon and masking layers. Under these circumstances, implanting source/drain or source/drain extension regions of the fin structures, may be difficult because ions directed to a surface of a given fin structure are shadowed by and adjacent fin or adjacent fins.
It is with respect to these and other considerations that the present disclosure is provided.